• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    FIELD OF THE INVENTION The present invention relates to an improved busy semiconductor package and a method for manufacturing the stacked busy semiconductor package. The semiconductor package for achieving the object of the present invention comprises a semiconductor chip (91) attached to the central recess (53) of the lower substrate (51); A wire 93 connecting one end of a wiring 59 on an upper surface of the lower substrate 51 to the semiconductor chip 91; An encapsulation member (97) surrounding the recess, the wire and the upper surface of the semiconductor chip (91); A lower through hole 55 having an upper portion wider than a lower portion at an outer side of the recess of the lower substrate 51; An upper substrate 71 having a conductive ball 95 mounted on the lower through hole 55 and an upper through hole 75 formed at a portion corresponding to the conductive ball 95 with an upper portion narrower than the lower portion is provided on the lower portion. It is adhered on the substrate 51. The BG semiconductor package according to the present invention can be stacked up and down, thereby increasing the packaging mounting density while maintaining the advantages of the BG package.
    公开号:KR19990086915A
    申请号:KR1019980020097
    申请日:1998-05-30
    公开日:1999-12-15
    发明作者:오성호
    申请人:김영환；현대반도체 주식회사；
    IPC主号:
    专利说明:

    Vijay A semiconductor package and its manufacturing method
    BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to semiconductor packages and methods for manufacturing the same, and more particularly, to a stackable business package and a method for manufacturing the same, which can produce a stacked type semiconductor package.
    As the demand for miniaturization and high performance of system equipment is increased, in order to cope with this, there is a high R & D desire for a high density semiconductor package in which more semiconductor chips are mounted in a semiconductor chip of the same size as before. A method for accommodating large-capacity semiconductor chips without increasing the size of the semiconductor package, the size being the same as the conventional, but the thickness is 1/2 of the conventional thin package (TSOP; Thin Small Outline Package) STACKED stacks of packages are commercially available.
    On the other hand, the conventional BG package has a wide lead pitch and no problems such as warpage of the external lead, so that it can meet the demand of multi-pinning, can be mass-produced, and has an excellent advantage of easy processing. Due to its structural characteristics, it is difficult to manufacture a stack package.
    Referring to the structure of the conventional BG semiconductor package as follows.
    Figure 1 shows a schematic longitudinal cross-sectional view of a conventional BG semiconductor package.
    That is, the substrate 1 having the plurality of through holes 3 and the interconnections 5 formed on the upper and lower surfaces of the substrate having a predetermined shape and filling the through holes 3. And a semiconductor chip 7 attached to a central portion of the upper surface of the substrate 1, a plurality of pads (not shown) formed on one surface of the semiconductor chip 7, and an upper surface of the upper surface of the substrate 1. A plurality of wires 9 connecting one of the wirings 5 to each other, a solder resist 11 covering a portion of the upper and lower surfaces of the substrate 1 and the upper and lower surfaces of the wiring 5, and the semiconductor. A molded body 13 surrounding the chip 7 and the wire 9 and solder balls 15 connected to the lower surface of each of the wirings 5 are provided.
    Since the BG package configured as described above has balls formed only on the bottom surface of the substrate due to its structural characteristics, there is a disadvantage in that a stack type package composed of several BG packages stacked up and down cannot be manufactured. Therefore, there is a disadvantage in that the mounting density is lower than other laminated packages having the same outer area.
    SUMMARY OF THE INVENTION An object of the present invention is to provide an improved BG semiconductor package capable of manufacturing a stackable BG package that has been devised to solve the conventional problems as described above.
    An object of the present invention is to provide an improved method for manufacturing a semiconductor package.
    SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a stacked Vishay IC package having high mounting density by using the improved vishay frequency package.
    In order to achieve the object of the present invention, an insulating substrate having a recess in the upper center portion, a plurality of lower through-holes in which the upper side inlet is wider than the lower side inlet in the insulating substrate except the recess, and the upper surface of the insulating substrate A lower substrate having conductive wiring formed in a predetermined shape on the substrate; A semiconductor chip attached to the center of the recess; A wire connecting the wiring and the semiconductor chip; An encapsulation member covering the wire, the semiconductor chip, and the recess; A plurality of conductive balls placed on each of the lower through holes; The upper substrate has a through portion at a position corresponding to the encapsulation member, and has a plurality of upper through holes formed at a position corresponding to the conductive ball, the upper inlet being narrower than the lower inlet. Provided is a semiconductor package to which a substrate is attached.
    1 is a conventional BG semiconductor package
    2 is a BG semiconductor package of the present invention
    Figure 3a is a plan view of the lower substrate of the present invention
    FIG. 3B is a longitudinal sectional view taken along line IIIb-IIIb of FIG. 3A
    Figure 4a is a plan view of the upper substrate of the present invention
    4B is a longitudinal sectional view taken along line IVb-IVb in FIG. 4A.
    5 is a longitudinal cross-sectional view of a stack business semiconductor package of the present invention;
    6A to 6D are manufacturing process diagrams showing a manufacturing process sequence of the BG semiconductor package of the present invention.
    *** Explanation of symbols for the main parts of the drawing ***
    51: lower substrate 52: insulated substrate
    53: recess 55: lower through hole
    57: thin metal film 59: wiring
    71: upper substrate 73: through part
    75: upper through hole 77: metal thin film
    91: semiconductor chip 93: wire
    95, 95a, 95b: conductive ball 97: sealing member
    100: printed circuit board 101: lower layer BIAG package
    111: Upper Biegie Packages
    In order to achieve the object of the present invention, an insulating substrate having a recess in the upper center portion, a plurality of lower through-holes in which the upper side inlet is wider than the lower side inlet in the insulating substrate except the recess, and the upper surface of the insulating substrate Preparing a lower substrate having conductive wiring formed in a predetermined shape on the substrate; Attaching a semiconductor chip to the recess; A wiring step of connecting one end of the semiconductor chip and the conductive wiring with a wire; Encapsulating the semiconductor chip, the wire, and the recess with an encapsulation member; Placing a conductive ball on the lower through hole; BG semiconductor comprising a step of attaching an upper substrate having a plurality of upper through holes formed in a lower portion than the lower portion at a corresponding position of the conductive ball on the lower substrate, and having a through portion at a position corresponding to the encapsulation member. Provided is a method for manufacturing a package.
    In order to achieve the object of the present invention, an insulating substrate having a recess in the upper center portion, a plurality of lower through-holes in which the upper side inlet is wider than the lower side inlet in the insulating substrate except the recess, and the upper surface of the insulating substrate A lower substrate having conductive wiring formed in a predetermined shape on the substrate; A semiconductor chip attached to the center of the recess; A wire connecting the wiring and the semiconductor chip; An encapsulation member covering the wire, the semiconductor chip, and the recess; A plurality of conductive balls placed on each of the lower through holes; The upper substrate is composed of a frame-shaped upper substrate bonded to the lower substrate, and the upper substrate has a through portion formed at a position corresponding to the encapsulation member, and the upper side inlet at the corresponding position of the conductive ball is lower than the lower side inlet. Manufacturing a plurality of BG semiconductor packages composed of a plurality of narrowly formed upper through holes; Placing a first BG semiconductor package, which is one of the plurality of BG packages, on a flat plate; On the first BG semiconductor package, a second BG semiconductor package, which is another BG semiconductor package, and the conductive balls of the first BG semiconductor package and the conductive balls of the second BG package are arranged to correspond to each other. Positioning process; A method of manufacturing a BIG semiconductor package including a process of reflowing a conductive ball of the first BG semiconductor package and a conductive ball of the second BG semiconductor package to be integrally connected to each other.
    The semiconductor package of the present invention can increase the package mounting density of a semiconductor chip by forming a conductive ball so as to protrude from the upper and lower surfaces of the substrate, and stacking a plurality of packages in the vertical direction. .
    The semiconductor package of the present invention is shown in FIG. 2. The semiconductor package of the present invention is characterized by assembling the package by adhering the lower substrate 51 and the upper substrate 71.
    First, the details of the lower substrate 51 and the upper substrate 71 will be described, and the structure of the semiconductor package of the present invention will be described.
    The lower substrate 51 is shown in plan view in FIG. 3A, and in FIG. 3B is a longitudinal sectional view along the line IIIb-IIIb in FIG. 3A. Like reference numerals in FIGS. 3A and 3B denote like parts. As shown in FIG. 3A, the lower substrate 51 is a flat insulating substrate 52, and a recess 53 is formed in the center of the upper surface of the insulating substrate 52. 53, a plurality of small lower through holes 55 are formed in the outer insulating substrate 52. In addition, as shown in Figure 3b, the shape of the lower through-hole 55 is formed in an inverted cone shape in which the upper inlet is wider than the lower inlet. 3A and 3B, a metal thin film 57 plated with a metal such as titanium is formed on the inner wall of the lower through hole 55. In addition, the upper surface of the lower substrate 51 is connected to the pad of the semiconductor chip and also connected to the conductive ball, the conductive wiring which is a signal path for transmitting a signal of the semiconductor chip to an external circuit (for example, a circuit on a printed circuit board) 59 is formed. In this case, the wiring 59 formed on the upper surface of the lower substrate 51 is formed to be electrically connected to the metal thin film 57 formed on the inner wall of the lower through hole 55. Accordingly, a conductive ball (not shown) to be placed in the lower through hole 55 may receive an external circuit (not shown) from the semiconductor chip (not shown) through the wiring 59 and the metal thin film 57. ) To deliver. However, the metal thin film 57 is not necessarily formed on the inner wall of the lower through hole 55. However, by forming the metal thin film 57, there is an effect of improving the electrical connection reliability between the conductive ball (not shown) and the wiring 59. When the conductive ball (not shown) is placed on the through hole 55 having no metal thin film on the inner wall, the insulating substrate 52 extends from the recess 53 to the lower through hole 55. The upper wiring may be directly connected to the conductive ball (not shown) to form an electrical signal path between the semiconductor chip and the wiring and the conductive ball. However, since the contact area between the wiring and the conductive ball is small, the reliability of the package may be degraded due to a poor connection between the wiring and the conductive ball. Therefore, the metal thin film 57 is coated on the inner wall of the lower through hole 55 to extend the wiring on the upper surface of the insulating substrate 52 to the inner wall of the lower through hole 55, thereby forming Since the contact reliability with the conductive balls is improved, it is preferable to form the metal thin film 57 on the inner wall of the lower through hole 55.
    The upper substrate 71 is shown in FIGS. 4A and 4B.
    A plan view of the upper substrate 71 is shown in FIG. 4A, and a longitudinal cross-sectional view along the IVb-IVb line of FIG. 4A is shown in FIG. 4B.
    In FIG. 4A, the upper substrate 71 is a frame type substrate having a through portion 73 at the center of the insulating substrate 72, and a plurality of small upper through holes in the insulating substrate 72 around the through portion. 75 is formed. A metal thin film 77 is formed on an inner wall of the upper through hole 75. Although the metal thin film 77 may not be formed on the inner wall of the upper through hole 75, the metal thin film 77 is more preferably formed. In addition, in the embodiment of FIG. 4A, a frame type upper substrate having a through portion 73 in the center is illustrated, but similarly to the lower substrate 51, a recess may be formed instead of the through portion 73. However, using an upper substrate having a recess has a disadvantage in that the overall thickness of the package after packaging is thicker than that of the upper substrate having a through portion. In addition, the through part 73 or the recess of the upper substrate is formed at a position corresponding to the sealing member to be described later.
    The upper through hole 75 in Figure 4b shows that the upper inlet is a cone formed wider than the lower inlet.
    Referring to Figure 2 the structure of the busy package of the present invention will be described. The semiconductor chip 91 is attached to the recess portion of the lower substrate 51 shown in FIG. 3A by an adhesive, and the pad (not shown) of the semiconductor chip and the wiring 59 of the lower substrate 51 are attached. The wire 93 connects one end. In addition, the upper substrate 71 of the frame type shown in FIG. 4A is bonded to the upper surface of the lower substrate 51. The lower inlet of the upper through hole 75 of the upper substrate 71 and the upper inlet of the lower through hole 55 of the lower substrate 51 are aligned to meet each other, and the upper and lower through holes 75, A conductive ball 95 is caught in 55. The conductive ball 95 is hung so as to protrude to the upper surface of the upper substrate 71 and also to protrude to the lower surface of the lower substrate 51. However, the conductive balls do not necessarily protrude to the upper and lower surfaces of the upper substrate 71 and the lower substrate 51, and the conductive balls 95 are exposed to the upper and lower portions of the upper and lower through holes 75 and 55. You may also The conductive ball 95 is made of solder having a low reflow temperature. In addition, the encapsulation member 97 covers the wire 93 and the semiconductor chip 91, and at this time, the upper surface of the encapsulation member 97 should be formed to be lower than the height of the conductive ball 95. Otherwise, when another busy package is stacked on the busy package of the present invention, the sealing member 97 causes the conductive balls of the upper BI package and the conductive balls of the lower BI package to be separated from each other. This is because signal transmission between the stacked packages becomes impossible.
    FIG. 5 shows the structure of a stacked BG semiconductor package manufactured using the BG semiconductor package of the present invention mounted on the printed circuit board 100. That is, the upper BI package 111 is placed on the lower BI package 101. The conductive balls 95a of the lower BG package and the conductive balls 95b of the upper BG package are connected to each other so that a semiconductor chip (not shown) in the upper BG package 111 and a semiconductor in the lower BG package 101 are connected. Signal transmission between chips (not shown) is possible. The conductive balls 95a of the lower business package 101 are connected to bond pads (not shown) on the printed circuit board 100, respectively.
    Next, the manufacturing method of the BG semiconductor package of the present invention will be described.
    The lower substrate 51 shown in Fig. 6A is produced. In the method of manufacturing the lower substrate, first, an insulating substrate 52 is prepared, a recess 53 is formed in the center of the upper surface of the insulating substrate 52, and a metal film is coated on the entire upper surface of the insulating substrate 52. Subsequently, lower through holes 55 are formed in a predetermined region. The lower through hole 55 is formed such that the diameter of the upper inlet is larger than the diameter of the lower inlet. As a result, the shape of the lower through hole 55 is an inverted cone. Therefore, the formation method may be easily formed by forming a mask pattern to expose only a region for forming the through hole 55 on the insulating substrate 50 and using wet etching. That is, when the wet etching method is applied to the exposed portion of the insulating substrate without being covered by the mask pattern, the upper portion of the insulating substrate 50 is more etched by the undercut phenomenon, and the lower portion is etched slowly. Conical through holes can be obtained. The inner walls of the through holes 55 are plated with metal thin films 57 such as titanium, respectively. Subsequently, the metal film on the upper surface of the insulating substrate 50 is patterned to form a wiring 59.
    As shown in FIG. 6B, an adhesive is applied to the center of the recess of the lower substrate 51, and a die bonding step of attaching the semiconductor chip 91 is performed. Next, a wiring process of connecting pads (not shown) of the semiconductor chip 91 and one end of the wires 59 to each other by wires is performed.
    Next, an encapsulation process is performed to cover the entirety of the wire 93, the semiconductor chip 91, and the recess 53 with the encapsulation member 97. In the encapsulation process, it is preferable to apply a molding process in terms of productivity and cost.
    Next, as illustrated in FIG. 6C, conductive balls 95 are placed on each of the plurality of through holes 55 of the lower substrate 51. The conductive ball 95 may be inserted into the through hole 55 by placing a plurality of conductive balls 95 on the lower substrate 51 and shaking them to the left and right so as to be seated in the through hole 55. have. Therefore, in the present invention, since a separate tool for mounting a conductive ball is not required, the apparatus investment cost is reduced and the package assembly process is easy.
    Next, as shown in FIG. 6D, the frame type upper substrate 71 shown in FIG. 3A or the upper substrate (not shown) having a recess in the center of the lower surface is bonded to the lower substrate 51 with an adhesive. In this case, an upper through hole 75 is formed in the upper substrate 71, and the upper through hole 75 is formed such that the diameter of the upper inlet is smaller than that of the lower inlet. The conductive ball 95 sandwiched between the upper through hole 75 of 71 and the lower through hole 55 of the lower substrate 51 does not fall out and is caught in the upper and lower through holes 55 and 75.
    In the method for manufacturing a stack type BG package using the BG semiconductor package of the present invention manufactured as described above, as shown in FIG. 5, the lower BG package 101 is placed on a flat plate and the bottom BG package The conductive ball 95a of the 101 and the conductive ball 95b of the upper BG package 111 are aligned so as to correspond to each other, and the upper BG package 111 is placed on the lower BG package 101. By reflowing, the conductive balls 95a and the conductive balls 95b are connected to each other, thereby manufacturing a stack of semiconductor packages.
    The BG semiconductor package according to the present invention does not need a separate tool for accurate alignment when placing the conductive ball on the package substrate, thereby reducing the production cost.
    The semiconductor package according to the present invention can be manufactured in a stack type because the conductive balls are protruded or exposed up and down, and thus a large number of semiconductor chips can be mounted while occupying the same area, thereby minimizing system equipment. It can be effective.
    In addition, since the stack busy semiconductor package according to the present invention has the advantage that the deformation of the external lead does not occur, there is an effect of improving the reliability of the semiconductor device.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] An insulating substrate having a recess in an upper center portion thereof, a plurality of lower through holes formed at an upper side of the insulating substrate other than the recessed portion in a wider area than a lower side inlet, a metal thin film formed on an inner wall of the lower through hole, A lower substrate composed of conductive wiring formed on a top surface of the insulating substrate in a predetermined shape;
    A semiconductor chip attached to an upper portion of the recess;
    A wire connecting one end of the wiring and the semiconductor chip;
    An encapsulation member covering the wire, the semiconductor chip, and the recess;
    A plurality of conductive balls placed on the metal thin films in the respective lower through holes;
    A frame-shaped body having a penetrating portion in a central portion, a plurality of upper through holes formed at a position corresponding to the conductive ball in the body and narrower than a lower inlet, and a metal thin film formed on an inner wall of the upper through hole. An upper substrate;
    And the upper substrate is attached on the lower substrate such that the lower inlet of the upper substrate and the upper inlet of the lower substrate face each other.
    [2" claim-type="Currently amended] 2. The BGA package of claim 1, wherein the conductive balls protrude upward and downward from the upper substrate and the lower substrate.
    [3" claim-type="Currently amended] An insulating substrate having a recess in an upper center portion thereof, a plurality of lower through holes formed on the insulating substrate except for the recess portion, and having lower openings wider than lower inlets, metal thin films formed on inner walls of the lower through holes; Preparing a lower substrate composed of conductive wiring formed on a top surface of the insulating substrate;
    Attaching a semiconductor chip to the recess;
    A wiring step of connecting one end of the semiconductor chip and the conductive wiring with a wire;
    Encapsulating the semiconductor chip, the wire, and the recess with an encapsulation member;
    Placing a conductive ball on the lower through hole;
    On the lower substrate, a frame-shaped body having a through portion in the center portion, a plurality of upper through-holes formed at a corresponding position of the conductive ball in the body narrower than the lower side inlet, and formed in the inner wall of the upper through hole And a step of attaching an upper substrate having a metal thin film.
    [4" claim-type="Currently amended] An insulating substrate having a recess in an upper center portion thereof, a plurality of lower through holes formed on the insulating substrate other than the recess portion, and having a lower inlet portion wider than a lower inlet portion, a metal thin film formed on an inner wall of the lower through hole; A lower substrate composed of conductive wiring formed on the upper surface of the insulating substrate in a predetermined shape;
    A semiconductor chip attached to the center of the recess;
    A wire connecting the wiring and the pad of the semiconductor chip;
    An encapsulation member covering the wire, the semiconductor chip, and the recess;
    A plurality of conductive balls placed on each of the lower through holes;
    A frame-shaped body having a penetrating portion in a central portion, a plurality of upper through holes formed at a position corresponding to the conductive ball in the body and narrower than a lower inlet, and a metal thin film formed on an inner wall of the upper through hole. Has an upper board,
    Manufacturing a plurality of BG semiconductor packages having the upper substrate attached to the lower substrate such that the lower inlet of the upper substrate and the upper inlet of the lower substrate face each other;
    Placing a first BG semiconductor package, which is one of the plurality of BG packages, on a flat plate;
    On the first BG semiconductor package, a second BG semiconductor package, which is another BG semiconductor package, and the conductive balls of the first BG semiconductor package and the conductive balls of the second BG package are arranged to correspond to each other. Positioning process;
    And a process for reflowing the conductive balls.
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    同族专利:
    公开号 | 公开日
    KR100271656B1|2000-11-15|
    US6191370B1|2001-02-20|
    JP2977557B1|1999-11-15|
    JPH11354683A|1999-12-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-05-30|Application filed by 김영환, 현대반도체 주식회사
    1998-05-30|Priority to KR1019980020097A
    1999-12-15|Publication of KR19990086915A
    2000-11-15|Application granted
    2000-11-15|Publication of KR100271656B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980020097A|KR100271656B1|1998-05-30|1998-05-30|Bga semiconductor package and fabrication method thereof|
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